*COMDECK  ECSCOM
 ECSCOM   CTEXT  ECS DEFINITIONS. 
COMECS    IFNE   IP.ECSB,0
          LIST   -R 
* 
*         SYMBOLS FOR ECS BUFFERING 
* 
*         INSTALLATION CHANGABLE PARAMETERS 
* 
IP.ECAUT  CEQU   0                 "0, AUTO ASSIGN ECS BUFFERS
IP.ELIB   CEQU   0                 "0,ECS RESIDENT LIBRARY
IP.ERES   CEQU   0                 "0,ECS RESIDENT FILES
IP.ESYS   CEQU   64D               ECS SYSTEM TABLE AREA LENGTH 
IP.EBUF   CEQU   16D               NUMBER OF PAGES IN A STANDARD BUFFER 
IP.EXDL   EQU    20                5MS DELAY FOR CONTROL POINT WITH 
*                                  A BUSY FNT 
* 
*         ECS INVARIANT SYMBOLS 
IP.EFLW   CEQU   20D
IP.EFTL   CEQU   6
IP.EICC   CEQU   36D               ICC AREA SIZE                         SC46187
* 
* 
*         ECS FIELD DEFINATIONS 
* 
IP.ECEL   EQU    64D               PRU LENGTH IN ECS
IP.EPAG   EQU    8D                NUMBER OF PRUS IN A PAGE 
IP.SSPH   EQU    2                 SYSTEM PAGE HEADER LENGTH
IP.SBPH   EQU    3                 SUBPAGE HEADER LENGTH
IP.SBPL   EQU    IP.ECEL/2-IP.SSPH/2  SUBPAGE LENGTH
IP.SYSL   EQU    3
IP.SYSL   EQU    3                 SYSTEM BUFFER DESC LENGTH
IP.CMBL   EQU    18D               LENGTH OF CM ADDRESS FIELD 
IP.ECBL   EQU    24D               LENGTH OF ECS ADDRESS FIELD
IP.SPBL   EQU    12D               LENGTH OF SUBPAGE FIELD
IP.LVLG   EQU    4                 LENGTH OF LEVEL NUMBER FIELD 
IP.PRUL   EQU    12D               LENGTH OF PRU FIELD
IP.RKCT   EQU    IP.SBPL*2-IP.SBPH*2-2  NB. OF ENTRIES IN AN AUX. SUBPG.
*         RECORD DESCRIPTOR TYPE FLAG 
E.SYSTF   EQU    0                 SYSTEM DESCRIPTOR
E.DATAF   EQU    8D                DATA DESCRIPTOR
E.LSTBND  EQU    0                 LIST LIMIT DESCRIPTOR
E.ENDLST  EQU    0                 END OF DESCR LIST
E.BEGLST  EQU    2                 BEGINNING OF DESCR LIST
E.LNKPTR  EQU    4                 LINK DESCRIPTOR
*         BUFFER HEADER FIELDS
E.SUBPTP  EQU    48D               SUBPAGE TYPE POSITION
E.DATATP  EQU    50D               BUFFER TYPE POSITION 
*         BUFFER TYPE (RELATIVE TO E.DATATP)
E.DEALOC  EQU    1                 DEALLOCATE DATA WHEN TRANSFERED
E.KEEP    EQU    0                 DATA NOT DEALLOCATED 
E.IOBUF   EQU    E.DEALOC+4        STANDARD I/O TYPE BUFFER 
E.ROPTN   EQU    40B               SPECIAL NO FLUSH OPTION
E.LIBRY   EQU    E.KEEP+10B        SYSTEM LIBRARY BUFFER
E.SWAP    EQU    E.KEEP+14B        ECS SWAP FILE
E.ECSRS   EQU    E.KEEP+20B        ECS RESIDENT FILE
E.AUXRN   EQU    E.KEEP+24B        RESIDENT RANDOM FILE AUXILARY
*         SUBPAGE POSITION (RELATIVE TO E.SUBPTP) 
E.EFIRST  EQU    1                 FIRST SUBPAGE BUFFER HEADER
  
  
*                MMF ECS LINK INSTALATION PARAMETERS
* 
  
IP.ECSLK  CEQU   0
*                            0 = NO MMF ECS LINK
*                            1 = ECSLINK CAN BE USED FOR MMF TRANSFERS
IP.LNKBF  CEQU   1
*                            NUMBER OF MMF ECS LINK BUFFERS DEFINED.
*                            ONE LINK BUFFER IS REQUIRED FOR EACH 
*                            LINK BETWEEN TWO DISTINCT MAINFRAMES.
 IP.MAXBL CEQU   1461B
*                            SIZE OF MAXIMUN X-BLOCK TO BE TRANSFERED 
*                            IN ONE ECS ACCESS. THIS CANNOT EXCEED 1461B
 IP.LNKMN CEQU   500B 
*                            MINIMUN ACCEPTABLE ECS LINK BUFFER LENGTH
* 
 IP.ECYC  CEQU   37B
* 
*                            CONTROLS PRIMARY RESTART CYCLE OF THE ECS
*                            LINK DRIVER. THE LINK DRIVER IS RESTARTED
*                            VIA MTR M.ICE CALL AT THE PRIMARY RATE 
*                            ONLY IF THERE IS WORK TO DO. THE FOLLOWING 
*                            RESTART TIMES ARE APPROXIMATE MILLISECONDS.
* 
*                             1B = 0.5 MS.     177B =   32 MS.
*                             3B =   1 MS.     377B =   64 MS.
*                             7B =   2 MS.     777B =  128 MS.
*                            17B =   4 MS.    1777B =  256 MS.
*                            37B =   8 MS.    3777B =  512 MS.
*                            77B =  16MS.     7777B = 1024 MS.
 IP.CYSTP CEQU   1           CONTROLS THE RATE AT WHICH THE LINK DRIVER 
*                            SLOWS ITS RESTART RATE WHEN LINK ACTIVITY
*                            IS LOW.
 IP.EIDLE CEQU   5
*                            CONTROLS THE NUMBER OF IDLE CYCLES ALLOWED 
*                            BEFORE THE LINK DRIVER DECIDES TO SLOW THE 
*                            RESTART RATE DUE TO INACTIVITY.
IP.ECLNK  CEQU   0
*                            1 = ALLOWS SIMULATION OF DUALS FOR ECS LINK
*                            TESTING ON ONE MAINFRAME. IP.LNKBF 
*                            MUST BE SET TO 2.
*                            0 = NO SIMULATION FOR DUAL TEST MODE 
* 
*                            MAXIMUM NUMBER OF LINK BUFFERS ALLOWED 
 N.LNKBUF EQU    IP.LNKBF 
 L.EBRT   EQU    N.LNKBUF*2+1  LENGTH OF ECS BUFFER RESERVATION TABLE 
 LE.EBRT  EQU    2           ECS BRT ENTRY LENGTH 
 L.CBRT   EQU    N.LNKBUF*2+1  LENGTH OF CMR RESIDENT BUFFER RESERVATION
*                            TABLE
 LE.CBRT  EQU    2           LENGTH OF ENTRIES IN THE TABLE 
 P.ECSCOM EQU    20B         ECS ADDRESS OF COMMON AREA POINTER 
  
  
**        ECS FLAG REGISTER FUNCTION MACROS 
* 
*         TESET  - THIS MACRO WILL TEST AND SET (IF POSSIBLE) THE FLAG
*                  REGISTER BIT SPECIFIED BY THE PARAMETER BIT. IF THE
*                  FLAG REGISTER IS SET THEN THE HALFEXIT WILL BE TAKEN 
* 
*         CLEAR  - THIS MACRO WILL UNCONDITIONALLY CLEAR BIT INDICATED
* 
*         SETFB  - THIS MACRO UNCONDITIONALLY SETS BIT INDICATED
* 
*                BIT - THE FLAG BIT NUMBER (0-17) TO BE FUNCTIONED
* 
 TESET    MACRO  BIT,HALFEXIT 
          SX0    B1 
          SB3    BIT
          LX0    B3,X0       POSITION FLAG BIT
          MX6    2
          LX6    24          POSITION TEST AND SET FUNCTION CODE
          BX0    X6+X0
          SA0    B0 
          RE     B1          STATUS FLAG BIT REGISTER 
-         EQ   HALFEXIT      BIT ALREADY SET
          ENDM
 SETFB    MACRO  BIT,HALFEXIT 
          SA2    SENDSET     FLAG REGISTER SET FUNCTION 
          SB2    BIT
          SX0    B1 
          LX0    B2,X0       POSITION FLAG BIT
          IX0    X0+X2
          SA0    B0 
          RE     B1          UNCONDITIONAL FLAG REGISTER SET
-         RJ   HALFEXIT      PARITY ERROR 
          ENDM
 CLEAR    MACRO  BIT,HALFEXIT 
          SA2    RECSET 
          SB2    BIT
          SX0    B1 
          LX0    B2,X0
          IX0    X0+X2
          SA0    B0 
          RE     B1          UNCONDITIONAL FLAG REGISTER CLEAR
-         RJ   HALFEXIT      PARITY ERROR 
          ENDM
  
  
**        ECS FLAG REGISTER BIT DEFINITIONS 
* 
  
 TN.LNK   EQU    0           MASTER ECS LINK BUFFER TABLE INTERLOCK 
 TN.BUF1  EQU    1           ECS LINK BUFFER STATUS BIT 
 TN.BUF2  EQU    2           ECS LINK BUFFER STATUS BIT 
 TN.BUF3  EQU    3           ECS LINK BUFFER STATUS BIT 
 TN.BUF4  EQU    4           ECS LINK BUFFER STATUS BIT 
          LIST   *
COMECS    ENDIF 
 ECSCOM   ENDX
