*COMDECK MACDEFS                                                         MACDEFS
                                                                         MACDEFS
*         COMDECK MACDEFS CONTAINS ASSEMBLER MACRO DEFINITIONS           MACDEFS
                                                                         MACDEFS
                                                                         MACDEFS
  
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * 
*                                                                     * 
*         ADDDDD    BINARY ADD - DOUBLE + DOUBLE = DOUBLE 
*         INPUT 
*             P1    OPERAND 1 UPPER HALF
*             P2    OPERAND 1 LOWER HALF
*             P3    OPERAND 2 UPPER HALF
*             P4    OPERAND 2 LOWER HALF
*         OUTPUT
*             P5    SUM UPPER HALF
*             P6    SUM LOWER HALF
*                                                                     * 
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * 
  
 ADDDDD   RMACRO 0,6,0
          FADD   I1,P1,P3 
          DADD   I2,P1,P3 
          FADD   I3,P2,P4 
          NORM   I4,,I1 
          FADD   I5,I2,I3 
          FADD   I6,I4,I5 
          NORM   I7,,I6 
          DADD   I8,I4,I5 
          NORM   I9,,I8 
          FADD   P5,I7,I9 
          DADD   P6,I7,I9 
          ENDR
  
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * 
*                                                                     * 
*         ADDSDD    BINARY ADD - SINGLE + DOUBLE = DOUBLE 
*         INPUT 
*             P1    OPERAND 1 UPPER HALF
*             P2    OPERAND 1 LOWER HALF
*             P3    OPERAND 2 
*         OUTPUT
*             P4    SUM UPPER HALF
*             P5    SUM LOWER HALF
*                                                                     * 
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * 
  
 ADDSDD   RMACRO 0,5,0
          FADD   I1,P1,P3 
          DADD   I2,P1,P3 
          NORM   I3,,I1 
          FADD   I4,I2,P2 
          FADD   I5,I3,I4 
          NORM   I6,,I5 
          DADD   I7,I3,I4 
          NORM   I8,,I7 
          FADD   P4,I6,I8 
          DADD   P5,I6,I8 
          ENDR
  
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * 
*                                                                     * 
*         DIVDDD    BINARY DIVIDE - DOUBLE/DOUBLE = DOUBLE
*         INPUT 
*             S1    ZERO DIVISOR EXIT 
*             P1    DIVIDEND UPPER HALF 
*             P2    DIVIDEND LOWER HALF 
*             P3    DIVISOR UPPER HALF
*             P4    DIVISOR LOWER HALF
*         OUTPUT
*             P5    QUOTIENT UPPER HALF 
*             P6    QUOTIENT LOWER HALF 
*                                                                     * 
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * 
  
 DIVDDD   RMACRO    1,6,0 
          ZR$    P3,,S1 
          FDIV   I1,P1,P3 
          FMUL   I2,I1,P3 
          FMUL   I3,I1,P4 
          FSUB   I4,P1,I2 
          DMUL   I5,I1,P3 
          DSUB   I6,P1,I2 
          NORM   I7,,I4 
          FADD   I8,I6,I7 
          FSUB   I9,P2,I5 
          FADD   I10,I8,I9
          FSUB   I11,I10,I3 
          FDIV   I12,I11,P3 
          FADD   I13,I1,I12 
          NORM   I14,,I13 
          DADD   I15,I1,I12 
          FADD   P5,I14,I15 
          DADD   P6,I14,I15 
          ENDR
  
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * 
*                                                                     * 
*         DIVDSD    BINARY DIVIDE - DOUBLE/SINGLE = DOUBLE
*         INPUT 
*             S1    ZERO DIVISOR EXIT 
*             P1    DIVIDEND UPPER HALF 
*             P2    DIVIDEND LOWER HALF 
*             P3    DIVISOR 
*         OUTPUT
*             P4    QUOTIENT UPPER HALF 
*             P5    QUOTIENT LOWER HALF 
*                                                                     * 
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * 
  
 DIVDSD   RMACRO    1,5,0 
          ZR$    P3,,S1 
          FDIV   I1,P1,P3 
          FMUL   I2,I1,P3 
          FSUB   I3,P1,I2 
          DMUL   I4,I1,P3 
          DSUB   I5,P1,I2 
          NORM   I6,,I3 
          FADD   I7,I5,I6 
          FSUB   I8,P2,I4 
          FADD   I9,I7,I8 
          FDIV   I10,I9,P3
          FADD   I11,I1,I10 
          NORM   I12,,I11 
          DADD   I13,I1,I10 
          FADD   P4,I12,I13 
          DADD   P5,I12,I13 
          ENDR
  
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * 
*                                                                     * 
*         DIVSDD    BINARY DIVIDE - SINGLE/DOUBLE = DOUBLE
*         INPUT 
*             S1    ZERO DIVISOR EXIT 
*             P1    DIVIDEND
*             P2    DIVISOR UPPER HALF
*             P3    DIVISOR LOWER HALF
*         OUTPUT
*             P4    QUOTIENT UPPER HALF 
*             P5    QUOTIENT LOWER HALF 
*                                                                     * 
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * 
  
 DIVSDD   RMACRO    1,5,0 
          ZR$    P2,,S1 
          FDIV   I1,P1,P2 
          FMUL   I2,I1,P2 
          FMUL   I3,I1,P3 
          FSUB   I4,P1,I2 
          DMUL   I5,I1,P2 
          DSUB   I6,P1,I2 
          NORM   I7,,I4 
          FADD   I8,I6,I7 
          FSUB   I9,I8,I5 
          FSUB   I10,I9,I3
          FDIV   I11,I10,P2 
          FADD   I12,I1,I11 
          NORM   I13,,I12 
          DADD   I14,I1,I11 
          FADD   P4,I13,I14 
          DADD   P5,I13,I14 
          ENDR
  
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * 
*                                                                     * 
*         DIVSSD    BINARY DIVIDE SINGE/SINGLE = DOUBLE 
*         INPUT 
*             S1    ZERO DIVISOR EXIT 
*             P1    DIVIDEND
*             P2    DIVISOR 
*         OUTPUT
*             P3    QUOTIENT UPPER HALF 
*             P4    QUOTIENT LOWER HALF 
*                                                                     * 
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * 
  
 DIVSSD   RMACRO    1,4,0 
          ZR$    P2,,S1 
          FDIV   I1,P1,P2 
          FMUL   I2,I1,P2 
          FSUB   I3,P1,I2 
          DMUL   I4,I1,P2 
          DSUB   I5,P1,I2 
          NORM   I6,,I3 
          FADD   I7,I5,I6 
          FSUB   I8,I7,I4 
          FDIV   I9,I8,P2 
          FADD   I10,I1,I9
          NORM   I11,,I10 
          DADD   I12,I1,I9
          FADD   P3,I11,I12 
          DADD   P4,I11,I12 
          ENDR
  
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * 
*                                                                     * 
*         DSPADD    SINGLE PRECISION DISPLAY CODE ADD 
*         INPUT 
*             P1    OPERAND 1 
*             P2    OPERAND 2 
*             S1    C.ZEROS 
*             S2    C.SIXES 
*         OUTPUT
*             P3    SUM 
*                                                                     * 
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * 
  
 DSPADD   RMACRO 2,3,0
          SLRBPK I1,,S1      SA4    C.ZEROS 
          IADD   I2,P1,P2    IX3    X1+X2 
          SLRBPK I3,,S2      SA5    C.SIZES 
          LIMP   I4,I3,I2    BX6    -X3*X5
          IADD   I5,I4,I2    IX7    X6+X3 
          SHL    I4,57       LX3    57
          ISUB   I6,I5,I1    IX0    X7-X4 
          IADD   P3,I6,I4    IX6    X0+X6 
          ENDR
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * 
* 
*         DSPSUB    SINGLE PRECISION DISPLAY CODE SUBTRACT
* 
*         INPUT 
*             P1    OPERAND 1 
*             P2    OPERAND 2 
*             S1    C.ZEROS 
*             S2    C.SIXES 
*         OUTPUT
*             P3    SUM 
* 
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * 
 DSPSUB   RMACRO 2,3,0
          SLRBPK I1,,S1      SA4 C.ZEROS
          ISUB   I2,P1,P2    IX3 X1-X2
          SLRBPK I3,,S2      SA5 C.SIXES
          LIMP   I4,I3,I2    BX6 -X3*X5 
          IADD   I5,I4,I2    IX7 X6+X3
          SHL    I4,57       LX3 57 
          ISUB   I6,I5,I1    IX0 X7-X4
          IADD   P3,I6,I4    IX6 X0+X6
          ENDR
  
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * 
*                                                                     * 
** NAME-  LDLFT MACRO                                                 * 
*                                                                     * 
** PURPOSE-                                                           * 
*      GENERATE CODE TO LOAD A  FIELD FROM THE LEFT SIDE OF A WORD.   * 
*      IRRELEVENT CHARACTER POSITIONS ARE ZEROED                      * 
*      RESULT LEFT AS IS- NOT ALIGNED IN REGISTER                     * 
*                                                                     * 
** CODE GENERATED-                                                    * 
*      SAI   K                                                        * 
*      MXO   A                                                        * 
*      BXJ   XO*XI                                                    * 
*      WHERE O IS DEFINED BY THE ASSEMBLER                            * 
*                                                                     * 
** PARAMETERS-                                                        * 
*      K=S1   ADDRESS OF SOURCE FIELD                                 * 
*      A=K1   SIZE OF FIELD IN BITS                                   * 
*      J=P1   REGISTER TO CONTAIN FIELD ON OUTPUT                     * 
*      I=P2   REGISTER TO CONTAIN SOURCE FIELD ADDRESS ON OUTPUT      * 
*                                                                     * 
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * 
  
 LDLFT    RMACRO 1,2,1
          SLRBPK P2,,S1      SAI   K
          MASK   I1,K1       MXO   A
          LAND   P1,P2,I1    BXJ   XO*XI
          ENDR
  
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * 
*                                                                     * 
** NAME-  LDLFT2 MACRO                                                * 
*                                                                     * 
** PURPOSE-                                                           * 
*      GENERATE CODE TO LOAD LEFT SIDE OF SECOND WORD OF DOUBLE       * 
*      PRECISION ITEM OR LAST WORD OF MULTIPLE PRECISION ITEM         * 
*      IRRELEVENT CHARACTER POSITIONS ARE ZEROED                      * 
*      RESULT LEFT AS IS- NOT ALIGNED IN REGISTER                     * 
*                                                                     * 
** CODE GENERATED-                                                    * 
*      SAJ   AI+B1   (B1=1)                                           * 
*      MXO   A                                                        * 
*      BXK   XO*XJ                                                    * 
*      WHERE O IS DEFINED BY THE ASSEMBLER                            * 
*                                                                     * 
** PARAMETERS-                                                        * 
*      A=K1   SIZE OF FIELD IN BITS                                   * 
*      I=P1   REGISTER CONTAINING ADDRESS OF PREVIOUS WORD LOADED     * 
*      K=P2   REGISTER TO CONTAIN FIELD ON OUTPUT                     * 
*      J=P3   REGISTER TO CONTAIN ADDRESS OF FIELD ON OUTPUT          * 
*                                                                     * 
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * 
  
 LDLFT2   RMACRO 0,3,1
          SLRAPB P3,P1,R1    SAJ   AI+B1
          MASK   I1,K1       MXO   A
          LAND   P2,I1,P3    BXK   XO*XJ
          ENDR
  
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * 
*                                                                     * 
** NAME-  LDMID MACRO                                                 * 
*                                                                     * 
** PURPOSE-                                                           * 
*      GENERATE CODE TO LOAD A FIELD FROM THE MIDDLE OF A WORD.        *
*      IRRELEVENT CHARACTER POSITIONS ARE ZEROED                      * 
*      RESULT LEFT AS IS- NOT ALIGNED IN REGISTER                     * 
*                                                                     * 
** CODE GENERATED-                                                    * 
*      SAI   K                                                        * 
*      MXO   A                                                        * 
*      LXO   B                                                        * 
*      BXJ   XO*XI                                                    * 
*      WHERE O IS DEFINED BY THE ASSEMBLER                            * 
*                                                                     * 
** PARAMETERS-                                                        * 
*      K=S1   ADDRESS OF SOURCE FIELD                                 * 
*      A=K1   SIZE OF FIELD IN BITS                                   * 
*      B=K2   SHIFT COUNT FOR MASK (USUALLY 60-6*BCP)                 * 
*      J=P1   REGISTER TO CONTAIN FIELD ON OUTPUT                     * 
*      I=P2   REGISTER TO CONTAIN SOURCE FIELD ADDRESS ON OUTPUT      * 
*                                                                     * 
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * 
  
 LDMID    RMACRO 1,2,2
          SLRBPK P2,,S1      SAI   K
          MASK   I1,K1       MXO   A
          SHL    I1,K2       LXO   B
          LAND   P1,P2,I1    BXJ   XO*XI
          ENDR
  
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * 
*                                                                     * 
** NAME-  LDRGT MACRO                                                 * 
*                                                                     * 
** PURPOSE-                                                           * 
*      GENERATE CODE TO LOAD A FIELD FROM THE RIGHT SIDE OF A WORD    * 
*      ZERO IRRELEVENT CHARACTER POSITIONS                            * 
*      RESULT LEFT AS IS- NOT ALIGNED IN REGISTER                     * 
*                                                                     * 
** CODE GENERATED-                                                    * 
*      SAI   K                                                        * 
*      MXO   A                                                        * 
*      BXJ   -XO*XI                                                   * 
*      WHERE O IS DEFINED BY THE ASSEMBLER                            * 
*                                                                     * 
** PARAMETERS-                                                        * 
*      K=S1   ADDRESS OF SOURCE FIELD                                 * 
*      A=K1   SIZE OF FIELD IN BITS                                   * 
*      J=P1   REGISTER TO CONTAIN FIELD ON OUTPUT                     * 
*      I=P2   REGISTER TO CONTAIN SOURCE FIELD ADDRESS ON OUTPUT      * 
*                                                                     * 
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * 
  
 LDRGT    RMACRO 1,2,1
          SLRBPK P2,,S1      SAI   K
          MASK   I1,K1       MXO   A
          LIMP   P1,P2,I1    BXJ   -XO*XI 
          ENDR
  
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * 
*                                                                     * 
** NAME- LDRTSPLT MACRO                                               * 
*                                                                     * 
** PURPOSE-                                                           * 
*      GENERATE CODE TO LOAD, ALIGN AND SPLIT OUT FIRST PART OF A DATA* 
*      FIELD                                                          * 
*                                                                     * 
** CODE GENERATED-                                                    * 
*      SAI   K                                                        * 
*      LXI   A                                                        * 
*      MXO   B                                                        * 
*      BXJ   -XO*XI                                                   * 
*      MXQ   C                                                        * 
*      BXL   XQ*XI                                                    * 
*      WHERE O AND Q ARE DEFINED BY THE ASSEMBLER                     * 
*                                                                     * 
** PARAMETERS-                                                        * 
*      K=S1   ADDRESS OF FIELD                                        * 
*      I=P1   ADDRESS OF FIELD (ON OUTPUT)                            * 
*      J=P2   REGISTER TO CONTAIN FIRST PART OF FIELD (ALIGNED)       * 
*      L=P3   REGISTER TO CONTAIN SECOND PART OF FIELD                * 
*      A=K1   SHIFT COUNT TO ALIGN FIELD (USUALLY 60-6(SIZEDIFF)      * 
*      B=K2   10-NUM OF CHARS IN FIRST PART OF FIELD (6*(BS+SIZEDIFF))* 
*      C=K3   NUMBER OF CHARS IN SECOND PART OF FIELD (6*(SR-10))     * 
*                                                                     * 
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * 
  
 LDRTSPLT RMACRO 1,3,3
          SLRBPK P1,,S1      SAI   K
          SHL    P1,K1       LXI   A
          MASK   I1,K2       MXO   B
          LIMP   P2,P1,I1    BXJ   -XO*XI 
          MASK   I2,K3       MXQ   C
          LAND   P3,I2,P1    BXL   XQ*XI
          ENDR
  
  
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * 
*                                                                     * 
** NAME-   LDSPLT2 MACRO                                              * 
*                                                                     * 
** PURPOSE-                                                           * 
*      GENERATE CODE TO LOAD SECOND WORD OF A DP ITEM (OR NEXT WORD   * 
*      OF A MULTIPLE PRECISION ITEM), SHIFT TO RIGHT-JUSTIFY IN A     * 
*      REGISTER AND APPEND TO PREVIOUSLY SPLIT ITEM                   * 
*                                                                     * 
** CODE GENERATED-                                                    * 
*      SAM   AI+B1                                                    * 
*      MXP   A                                                        * 
*      BXQ   XP*XM                                                    * 
*      LXQ   B                                                        * 
*      BXL   XQ+XK                                                     *
*      WHERE M, P AND Q ARE DEFINED BY THE ASSEMBLER                  * 
*                                                                     * 
** PARAMETERS-                                                        * 
*      I=P1   REGISTER CONTAINING ADDRESS OF PREVIOUSLY LOADED WORD   * 
*      K=P2   REGISTER CONTAINING SPLIT-OUT PART  OF PREVIOUS WORD    * 
*      L=P3   REGISTER TO CONTAIN FIELD ON OUTPUT                     * 
*      A=K1   SIZE OF FIELD LYING IN SECOND WORD                      * 
*      B=K2   SHIFT COUNT TO ALIGN FIELD                              * 
*                                                                     * 
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * 
  
 LDSPLT2  RMACRO 0,3,2
          SLRAPB I1,P1,R1    SAM   AI+B1
          MASK   I2,K1       MXP   A
          LAND   I3,I2,I1    BXQ   XP*XM
          SHL    I3,K2       LXQ   B
          LOR    P3,I3,P2    BXL   XQ+XK
          ENDR
  
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * 
* 
*         LDSUB     LOAD SUBSCRIPTED ITEM 
*         INPUT 
* 
*             S1    BIASED FWA OF ITEM TO BE LOADED 
*             P1    CHARACTER OFFSET
*         OUTPUT
*             P2    FIRST WORD OF ITEM
* 
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * 
  
 LDSUB    RMACRO 1,2,0
          SXBPK  I1,,314632B
          IMUL   I2,P1,I1 
          SHR    I2,20
          SLRXPK P2,I2,S1 
          ENDR
  
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * 
* 
*         LDSUBWO   LOAD SUBSCRIPTED ITEM AND COMPUT OFFSET MOD 10
*         INPUT 
*             S1    C.TNTH
*             S2    BIASED FWA OF ITEM TO BE LOADED 
*             P1    CHARACTER OFFSET
*         OUTPUT
*             P2    CHARACTER OFFSET MOD 10 
*             P3    FIRST WORD OF ITEM
* 
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * 
  
 LDSUBWO  RMACRO 2,3,0
          SLRBPK I1,,S1 
          IMUL   I2,P1,I1 
          MASK   I3,36
          LIMP   I4,I2,I3 
          SHL    I4,4 
          LIMP   I5,I2,I3 
          ISUB   P2,I4,I5 
          SHR    I2,24
          SHR    P2,22
          SLRXPK P3,I2,S2 
          ENDR
  
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * 
*                                                                     * 
** NAME-  LD2LFSPL MACRO                                              * 
*                                                                     * 
** PURPOSE-                                                           * 
*      LOAD, ALIGN AND SPLIT FIRST PART OF SECOND WORD OF DP ITEM OR  * 
*      NEXT WORD OF MULTIPLE PRECISION ITEM)                          * 
*                                                                     * 
** CODE GENERATED-                                                    * 
*      SAL   AS+B1                                                    * 
*      LXL   A                                                        * 
*      MXO   B                                                        * 
*      BXM   -XO*XL                                                   * 
*      MXQ   C                                                        * 
*      BXN   XQ*XL                                                    * 
*      WHERE O AND Q ARE DEFINED  BY THE ASSEMBLER                    * 
*                                                                     * 
** PARAMETERS-                                                        * 
*      S=P1   REGISTER CONTAINING ADDRESS OF PREVIOUSLY LOADED WORD   * 
*      L=P2   REGISTER TO CONTAIN ADDRESS OF CURRENT WORD ON OUTPUT   * 
*      M=P3   REGISTER TO CONTAIN FIRST PART OF WORD ON OUTPUT        * 
*      N=P4   REGISTER TO CONTAIN SECOND PART OF WORD ON OUTPUT       * 
*      A=K1   SHIFT COUNT TO ALIGN FIELD                              * 
*      B=K2   60-6*SIZE OF FIRST PART OF FIELD                        * 
*      C=K3   SIZE OF SECOND PART OF FIELD                            * 
*                                                                     * 
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * 
  
 LD2LFSPL RMACRO 0,4,3
          SLRAPB P2,P1,R1    SAL   AS+B1
          SHL    P2,K1       LXL   A
          MASK   I1,K2       MXO   B
          LIMP   P3,P2,I1    BXM   -XO*XL 
          MASK   I2,K3       MXQ   C
          LAND   P4,I2,P2    BXN   XQ*XL
          ENDR
  
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * 
*                                                                     * 
** NAME-  LMS2 MACRO                                                  * 
*                                                                     * 
** PURPOSE-                                                           * 
*      GENERATE CODE TO MOVE SECOND WORD OF DOUBLE PRECISION ITEM TO  * 
*      SECOND WORD OF DOUBLE PRECISION ITEM, OR NEXT WORD OF MULTIPLE * 
*      PRECISION ITEM TO NEXT WORD OF MULTIPLE PRECISION ITEM         * 
*                                                                     * 
** CODE GENERATED-                                                    * 
*      SAM   AJ+B1                                                    * 
*      BXL   XM                                                       * 
*      SAL   AN+B1                                                    * 
*      WHERE M AND L ARE DEFINED BY THE ASSEMBLER                     * 
*                                                                     * 
** PARAMETERS-                                                        * 
*      J=P1   AJ CONTAINS ADDRESS OF FIRST WORD OF SOURCE FIELD       * 
*      N=P2   AN CONTAINS ADDRESS OF FIRST WORD OF RECEIVING FIELD    * 
*                                                                     * 
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * 
  
 LMS2     RMACRO 0,2,0
          SLRAPB I1,P1,R1    SAM   AJ+B1
          XMIT   I2,I1       BXL   XM 
          SSRAPB I2,P2,R1    SAL   AN+B1
          ENDR
  
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * 
*                                                                     * 
** NAME-  MVSPLWD MACRO                                               * 
*                                                                     * 
** PURPOSE-                                                           * 
*      GENERATE CODE TO LOAD, SPLIT AND STORE CONSECUTIVE FULL WORDS  * 
*      (I.E. THE INTERIOR WORDS OF AN EP ITEM).                       * 
*                                                                     * 
** CODE GENERATED-                                                    * 
*            SBL   A                                                  * 
*            MXO   C                                                  * 
*      LOOP  BSS   0                                                   *
*            SAI   AI+B1                                              * 
*            SBL   BL-B1                                              * 
*            LXI   B                                                  * 
*            BXM   -XO*XI                                             * 
*            BXK   XM+XJ                                              * 
*            BXJ   XO*XI                                              * 
*            SAK   AK+1                                               * 
*            NE    BL,LOOP                                            * 
*      WHERE L, O,AND M ARE DEFINED BY THE ASSEMBLER                  * 
*                                                                     * 
** PARAMETERS-                                                        * 
*      I=P1   REGISTER CONTAINING ADDRESS OF PREVIOUSLY LOADED WORD   * 
*             ON OUTPUT CONTAINS ADDRESS OF LAST WORD LOADED.         * 
*      J=P2   REGISTER CONTAINING PREVIOUSLY SPLIT-OUT PORTION OF      *
*             LAST WORD LOADED TO APPEND TO FIRST WORD THIS MACRO     * 
*             LOADS.                                                  * 
*             ON OUTPUT CONTAINS SPLIT-OUT PORTION OF LAST WORD THIS  * 
*             MACRO LOADS                                             * 
*      K=P3   REGISTER CONTAINING ADDRESS OF LAST WORD STORED INTO    * 
*             ON OUTPUT CONTAINS ADDRESS OF LAST WORD THIS MACRO      * 
*             STORES INTO.                                            * 
*      LOOP=S1   NEXT LOCAL LABEL NUMBER                               *
*      A=S2   COUNT OF WORDS TO PROCESS                                *
*      B=K1   SHIFT COUNT TO ALIGN FIELDS                              *
*      C=K2   60-B                                                     *
*                                                                     * 
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * 
  
 MVSPLWD  RMACRO 2,3,2
          HOLDR  P1 
          HOLDR  P2 
          HOLDR  P3 
          SBBPK  I1,,S2      SBL   A
          MASK   I2,K2             MXO   C
          LABEL$ S1          LOOP  BSS   0
          HOLDR  I1 
          SLRAPB P1,P1,R1          SAI   AI+B1
          SBBMB  I1,I1,R1          SBL   BL-B1
          SHL    P1,K1             LXI   B
          LIMP   I3,P1,I2          BXM   -XO*XI 
          LOR    P3,I3,P2          BXK   XM+XJ
          LAND   P2,I2,P1          BXJ   XO*XI
          SSRAPK P3,P3,1           SAK   AK+1 
          NE$    I1,,S1            NE    BL,LOOP
          RFREE  P1 
          RFREE  P2 
          RFREE  P3 
          RFREE  I1 
          ENDR
  
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * 
*                                                                     * 
*         MULTDDD   BINARY MULTIPLY - DOUBLE * DOUBLE = DOUBLE
*         INPUT 
*             P1    OPERAND 1 UPPER HALF
*             P2    OPERAND 1 LOWER HALF
*             P3    OPERAND 2 UPPER HALF
*             P4    OPERAND 2 LOWER HALF
*         OUTPUT
*             P5    PRODUCT UPPER HALF
*             P6    PRODUCT LOWER HALF
*                                                                     * 
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * 
  
 MULTDDD  RMACRO 0,6,0
          FMUL   I1,P2,P3    FX5    X2*X3 
          FMUL   I2,P1,P4    FX6    X1*X4 
          FADD   I3,I1,I2    FX7    X5+X6 
          FMUL   I4,P1,P3    FX0    X1*X3 
          DMUL   I5,P1,P3    FX6    X1*X3 
          FADD   I6,I5,I3    FX5    X7+X6 
          FADD   P5,I6,I4    FX6    X5+X0 
          DADD   P6,I6,I4    FX7    X5+X0 
          ENDR
  
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * 
*                                                                     * 
*         MULTSDD   BINARY MULTIPLY - SINGLE * DOUBLE = DOUBLE
*         INPUT 
*             P1    OPERAND 1  1
*             P2    OPERAND 2 UPPER HALF
*             P3    OPERAND 2"LOWER HALF
*         OUTPUT
*             P4    PRODUCT UPPER HALF
*             P5    PRODUCT LOWER HALF
*                                                                     * 
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * 
  
 MULTSDD  RMACRO 0,5,0
          FMUL   I1,P1,P3    FX0    X1*X4 
          DMUL   I2,P1,P2    DX5    X1*X3 
          FMUL   I3,P1,P2    FX6    X1*X3 
          FADD   I4,I1,I2    FX7    X0+X5 
          FADD   P4,I4,I3    FX4    X6+X7 
          DADD   P5,I4,I3    FX5    X6+X7 
          ENDR
  
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * 
*                                                                     * 
*         MULTSSD   BINARY MULTIPLY - SINGLE * SINGLE = DOUBLE
*         INPUT 
*             P1    OPERAND 1 
*             P2    OPERAND 2 
*         OUTPUT
*             P3    PRODUCT UPPER HALF
*             P4    PRODUCT LOWER HALF
*                                                                     * 
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * 
  
 MULTSSD  RMACRO 0,4,0
          FMUL   P3,P1,P2    FX3    X1*X2 
          DMUL   P4,P1,P2    DX4    X1*X2 
          ENDR
  
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * 
*                                                                     * 
** NAME-  MVSTR MACRO                                                 * 
*                                                                     * 
** PURPOSE-                                                           * 
*      GENERATE CODE TO MOVE LOAD X-REG TO STORE X-REG AND STORE      * 
*                                                                     * 
** CODE GENERATED-                                                    * 
*      BXI   XJ                                                       * 
*      SAI   K                                                        * 
*                                                                     * 
** PARAMETERS-                                                        * 
*      K=S1   ADDRESS AT WHICH TO STORE                               * 
*      J=P1   ON INPUT XJ CONTAINS WORD TO STORE                      * 
*      I=P2   ON EXIT AI CONTAINS ADDRESS OF THE WORD STORED INTO     * 
*                                                                     * 
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * 
  
 MVSTR    RMACRO 1,2,0
          XMIT   P2,P1       BXI   XJ 
          SSRBPK P2,,S1      SAI   K
          ENDR
  
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * 
*                                                                     * 
** NAME-  STLFT MACRO                                                 * 
*                                                                     * 
** PURPOSE-                                                           * 
*      GENERATE CODE TO STORE A DATA FIELD INTO THE LEFT SIDE OF A WORD*
*      BACKGROUND CHARACTERS ARE RETAINED IN RESULTANT WORD           * 
*      FIELD TO BE STORED MUST ALREADY BE ALIGNED                     * 
*                                                                     * 
** CODE GENERATED-                                                    * 
*      SAU   K                                                        * 
*      MXO   A                                                        * 
*      BXS   -XO*XU                                                   * 
*      BXJ   XS+XI                                                     *
*      SAJ   AU                                                       * 
*      WHERE O, U AND S ARE DEFINED BY THE ASSEMBLER                  * 
*                                                                     * 
** PARAMETERS-                                                        * 
*      K=S1   ADDRESS OF RECEIVING FIELD                              * 
*      A=K1   SIZE OF RECEIVING FIELD IN BITS                         * 
*      I=P1   VIRTUAL REGISTER THAT CONTAINS FIELD TO STORE           * 
*      J=PI   STORE REGISTER                                          * 
*                                                                     * 
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * 
  
 STLFT    RMACRO 1,2,1
          SLRBPK I1,,S1      SAU   K
          MASK   I2,K1       MXO   A
          LIMP   I3,I1,I2    BXS   -XO*XU 
          LOR    P2,I3,P1    BXJ   XS+XI
          SSRAPB P2,I1       SAJ   AU 
          ENDR
  
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * 
*                                                                     * 
** NAME-  STLFT2 MACRO                                                * 
*                                                                     * 
** PURPOSE-                                                           * 
*      GENERATE CODE TO STORE THE SECOND WORD OF A DOUBLE PRECISION   * 
*      ITEM, OR THE LAST WORD OF A MULTIPLE PRECISION ITEM            * 
*      BACKGROUND CHARACTERS ARE RETAINED IN RESULTANT WORD           * 
*      FIELD TO BE STORED MUST ALREADY BE ALIGNED                     * 
*                                                                     * 
** CODE GENERATED-                                                    * 
*      SAK   AI+B1                                                    * 
*      MXO   A                                                        * 
*      BXL   -XO*XK                                                   * 
*      BXM   XL+XJ                                                     *
*      SAM   AK                                                       * 
*      WHERE O,L AND K ARE DEFINED BY THE ASSEMBLER                   * 
*                                                                     * 
** PARAMETERS-                                                        * 
*      A=K1   SIZE OF RECEIVING FIELD                                 * 
*      I=P1   ADDRESS OF LAST WORD STORED INTO                        * 
*      J=P2   REGISTER CONTAINING FIELD TO STORE                      * 
*      M=P3   ADDRESS OF RECEIVING FIELD ON OUTPUT                    * 
*                                                                     * 
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * 
  
 STLFT2   RMACRO 0,3,1
          SLRAPB I1,P1,R1    SAK   AI+B1
          MASK   I2,K1       MXO   A
          LIMP   I3,I1,I2    BXL   -XO*XK 
          LOR    P3,I3,P2    BXM   XL+XJ
          SSRAPB P3,I1       SAM   AK 
          ENDR
  
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * 
*                                                                     * 
** NAME-  STMID MACRO                                                 * 
*                                                                     * 
** PURPOSE-                                                           * 
*      GENERATE CODE TO STORE A DATA FIELD INTO THE MIDDLE OF A WORD  * 
*      BACKGROUND CHARACTERS ARE RETAINED IN RESULTANT WORD           * 
*      FIELD TO BE STORED MUST ALREADY BE ALIGNED                     * 
*                                                                     * 
** CODE GENERATED-                                                    * 
*      SAU   K                                                        * 
*      MXO   A                                                        * 
*      LXO   B                                                        * 
*      BXS   -XO*XU                                                   * 
*      BXJ   XS+XI                                                     *
*      SAJ   AU                                                       * 
*      WHERE O, U AND S ARE DEFINED BY THE ASSEMBLER                  * 
*                                                                     * 
** PARAMETERS-                                                        * 
*      K=S1   ADDRESS OF RECEIVING FIELD                              * 
*      A=K1   SIZE OF RECEIVING FIELD IN BITS                         * 
*      B=K2   SHIFT COUNT (USUALLY 60-6*BCP)                          * 
*      I=P1   VIRTUAL REGISTER THAT CONTAINS FIELD TO STORE           * 
*      J=PI   STORE REGISTER                                          * 
*                                                                     * 
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * 
  
 STMID    RMACRO 1,2,2
          SLRBPK I1,,S1      SAU   K
          MASK   I2,K1       MXO   A
          SHL    I2,K2       LXO   B
          LIMP   I3,I1,I2    BXS   -XO*XU 
          LOR    P2,I3,P1    BXJ   XS+XI
          SSRAPB P2,I1       SAJ   AU 
          ENDR
  
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * 
*                                                                     * 
** NAME-  STRGT MACRO                                                 * 
*                                                                     * 
** PURPOSE-                                                           * 
*      GENERATE CODE TO STORE A DATA FIELD INTO THE RIGHT SIDE OF A   * 
*      WORD                                                           * 
*      BACKGROUND CHARACTERS ARE RETAINED                             * 
*      FIELD TO BE STORED MUST ALREADY BE ALIGNED                     * 
*                                                                     * 
** CODE GENERATED-                                                    * 
*      SAU   K                                                        * 
*      MXO   A                                                        * 
*      BXS   XO*XU                                                    * 
*      BXJ   XI+XS                                                     *
*      SAJ   AU                                                       * 
*      WHERE U, O AND S ARE DEFINED BY THE ASSEMBLER                  * 
*                                                                     * 
** PARAMETERS-                                                        * 
*      K=S1   ADDRESS OF RECEIVING FIELD                              * 
*      A=K1   SIZE OF RECEIVING FIELD IN BITS                         * 
*      I=P1   REGISTER THAT CONTAINS FIELD TO STORE                   * 
*      J=P2   STORE REGISTER                                          * 
*                                                                     * 
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * 
  
 STRGT    RMACRO 1,2,1
          SLRBPK I1,,S1      SAU   K
          MASK   I2,K1       MXO   A
          LAND   I3,I2,I1    BXS   XO*XU
          LOR    P2,I3,P1    BXJ   XI+XS
          SSRAPB P2,I1
          ENDR
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *  * * *
* 
*         STSUB     SUBSCRIPTED STORE 
*         INPUT 
*             S1    BIASED FWA OF DISTINATION 
*             P1    CHARACTER OFFSET
*             P2    REGISTER TO BE STORED 
* 
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * 
  
 STSUB    RMACRO 1,2,0
          SXBPK  I1,,314632B
          IMUL   I2,P1,I1 
          SHR    I2,20
          XMIT   I3,P2
          SSRXPK I3,I2,S1 
          ENDR
  
  
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * 
*                                                                     * 
*         SUBDDD    BINARY SUBTRACT - DOUBLE - DOUBLE = DOUBLE
*         INPUT 
*             P1    OPERAND 1 UPPER HALF
*             P2    OPERAND 1 LOWER HALF
*             P3    OPERAND 2 UPPER HALF
*             P4    OPERAND 2 LOWER HALF
*         OUTPUT
*             P5    DIFFERENCE UPPER HALF 
*             P6    DIFFERENCE LOWER HALF 
*                                                                     * 
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * 
  
 SUBDDD   RMACRO 0,6,0
          FSUB   I1,P1,P3 
          DSUB   I2,P1,P3 
          FSUB   I3,P2,P4 
          NORM   I4,,I1 
          FADD   I5,I2,I3 
          FADD   I6,I4,I5 
          NORM   I7,,I6 
          DADD   I8,I4,I5 
          NORM   I9,,I8 
          FADD   P5,I7,I9 
          DADD   P6,I7,I9 
          ENDR
  
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * 
*                                                                     * 
*         SUBDSD    BINARY SUBTRACT - DOUBLE - SINGLE = DOUBLE
*         INPUT 
*             P1    OPERAND 1 UPPER HALF
*             P2    OPERAND 1 LOWER HALF
*             P3    OPERAND 2 
*         OUTPUT
*             P4    DIFFERENCE UPPER HALF 
*             P5    DIFFERENCE LOWER HALF 
*                                                                     * 
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * 
  
 SUBDSD   RMACRO 0,5,0
          FSUB   I1,P1,P3 
          DSUB   I2,P1,P3 
          NORM   I3,,I1 
          FADD   I4,I2,P2 
          FADD   I5,I3,I4 
          NORM   I6,,I5 
          DADD   I7,I3,I4 
          NORM   I8,,I7 
          FADD   P4,I6,I8 
          DADD   P5,I6,I8 
          ENDR
  
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * 
*                                                                     * 
*         SUBSDD    BINARY SUBTRACT - SINGLE - DOUBLE = DOUBLE
*         INPUT 
*             P1    OPERAND 1 
*             P2    OPERAND 2 UPPER HALF
*             P3    OPERAND 2 LOWER HALF
*         OUTPUT
*             P4    DIFFERENCE UPPER HALF 
*             P5    DIFFERENCE LOWER HALF 
*                                                                     * 
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * 
  
 SUBSDD   RMACRO 0,5,0
          FSUB   I1,P1,P2 
          DSUB   I2,P1,P2 
          NORM   I3,,I1 
          FSUB   I4,I2,P3 
          FADD   I5,I3,I4 
          NORM   I6,,I5 
          DADD   I7,I3,I4 
          NORM   I8,,I7 
          FADD   P4,I6,I8 
          DADD   P5,I6,I8 
          ENDR
  
  
  
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * 
*                                                                     * 
** NAME- SPLITIT MACRO                                                * 
*                                                                     * 
** PURPOSE-                                                           * 
*      GENERATE CODE TO SPLIT A FIELD IN 1 REG INTO 2 FIELDS IN 2 REGS* 
*                                                                     * 
** CODE GENERATED-                                                    * 
*         MXI    A                                                    * 
*         LXJ    B                                                    * 
*         MXK    C                                                    * 
*         BXL    -XI*XJ                                               * 
*         BXM    XK*XJ                                                * 
*         WHERE I AND K ARE DEFINED BY THE ASSEMBLER                  * 
*                                                                     * 
** PARAMETERS-                                                        * 
*      J=P1   REGISTER CONTAINING FIELD TO SPLIT                      * 
*      L=P2   REGISTER TO CONTAIN LEFT-MOST CHARS OF FIELD            * 
*      M=P2   REGISTER TO CONTAIN RIGHT-MOST CHARS OF FIELD           * 
*       A=K1   10-NO OF CHARS WANTED IN P2                            * 
*      B=K2   LEFT SHIFT COUNT TO ALIGN REGISTER                      * 
*      C=K3   NO OF CHARS WANTED IN P3                                * 
*                                                                     * 
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * 
  
 SPLITIT  RMACRO 0,3,3
          MASK   I1,K1       MXI   A
          SHL    P1,K2       LXJ   B
          MASK   I2,K3       MXK   C
          LIMP   P2,P1,I1    BXL   -XI*XJ 
          LAND   P3,P1,I2    BXM   XK*XJ
          ENDR
