*COMDECK PILMT                                                           CC4
         NAM     PILMT                                                   CC4
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *  CC4
*                                                                     *  CC4
*                        PILMT                                        *  CC4
*        FINDS THE UPPER LIMIT OF THE MEMORY                          *  CC4
*                                                                     *  CC4
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *  CC4
*                                                                        CC4
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *  CC4
*                                                                     *  CC4
** OVERVIEW                                                           *  CC4
*                                                                     *  CC4
*     IF THE PAGE REGISTER EXISTS THEN A MOS MEMORY MACHINE IS        *  CC4
*     IN USE ELSE A CORE MACHINE IS ASSUMED.  FOR THE CORE MACHINE    *  CC4
*     THE WE USE THE RAP AROUND TO TEST FOR THE EXISTENCE OF THE      *  CC4
*     UPPER 16K MEMORY MODULE. FOR A MOS MACHINE THE STORAGE PARITY   *  CC4
*     ERROR IS USED TO DETECT THE FIRST NON-EXISTENT 16K MODULE.      *  CC4
*     STORAGE PARITY IS NOT PREDICTABLE FOR READ MEMORY INSTRUCTIONS. *  CC4
*     THIS PROGRAM ASSUMES THE PAGE REGISTERS TO BE INITIALIZED       *  CC4
*     FOR SEQUENTIAL MEMORY ASSIGNMENT FOR FIRST 65K AND THAT PAGE    *  CC4
*     MODE ZERO IS SELECTED.  NOTE THAT THIS ROUTINE MAY NOT BE       * 
*     LINKED FROM LOCATION F800 TO FFFF.                              * 
*                                                                     *  CC4
** INPUT       NONE                                                   *  CC4
*                                                                     *  CC4
** OUTPUT      J1CORESIZE     WORD1 = HIGHEST PAGE VALUE              *  CC4
*                             WORD2 = HIGHEST PAGE NUMBER AND         *  CC4
*                                       DISPLACEMENT (HIGHEST ADDRESS *  CC4
*                                       FOR ANY CORE MAPPING          *  CC4
*                                                                     *  CC4
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *  CC4
         SPC     3                                                       CC4
         ENT     PILMT                                                   CC4
         EXT     J1CORESIZE                                              CC4
*                                                                        CC4
         EQU     SI16KI($8)   PAGE REGISTER INCREMENT FOR 16K            CC4
SITLOC    NUM    $F801        LOCATION FOR MEMORY TEST
         EQU     SIPMAX($40)  MAX PAGE VALUE (128K)                      CC4
         EQU     SIPMIN($18)  MINIMUM SYSTEM (48K)                       CC4
          EQU    SISVPG($1F)  PAGE REGISTER USED IN TEST
SIPAGE   NUM     $18                                                     CC4
SITPN     NUM    $F800        PAGE NUMBER AND BANK FOR TEST LOCATION
SI48K    NUM     $BFFE        48K CORE LIMIT                             CC4
SI65K    NUM     $FFFD        65K CORE LIMIT                             CC4
SC000     NUM    $0           SAVE LOC C000 FOR CORE MACHINE
*                                                                        CC4
PILMT    NOP                                                             CC4
          LDA+   $C000        GET CONTENTS OF C000
          STA*   SC000        SAVE CONTENTS OF LOC C000 
         ENA     SIPMIN       INITIAL TEST PAGE                          CC4
         STA*    SIPAGE       - MINIMUM CORE MODULE                      CC4
         LDA*    SITPN        TEST PAGE NUMBER AND BANK                  CC4
         RPR     A            READ PAGE REGISTER                         CC4
          AND    =N$1FF                                                  CC4
          INA    -SISVPG      EXPECTED RESPONSE 
         SAZ     PILMT2       SKIP IF MOS MEMORY                         CC4
*                                                                        CC4
* * * CORE MEMORY MACHINE                                                CC4
*                                                                        CC4
          LDA*   SC000        GET CONTENTS OF SAVE LOCATION 
          STA+   $C000        RESTORE CONTENTS OF LOCATION C000 
         LDA*    (SITLOC)                                                CC4
         SUB-    1            CHECK FOR RAP AROUND                       CC4
         ENQ     SIPMIN+SI16KI  65K LIMIT                                CC4
         SAZ     PILMT1       SKIP IF 48K                                CC4
         STQ*    SIPAGE                                                  CC4
PILMT1   JMP*    PILMT3                                                  CC4
*                                                                        CC4
* * * MOS MEMORY MACHINE                                                 CC4
*                                                                        CC4
PILMT2   SPE     0            CLEAR ANY PARITY ERROR LEFT 
PILM25   LDA*    SIPAGE       GET PAGE ADDRESS
         ORA*    SITPN        INCLUDE TEST PAGE REGISTER AND BANK        CC4
         WPR     A            WRITE PAGE REGISTER                        CC4
*                                                                        CC4
         LDQ*    (SITLOC)     SAVE TEST LOCATION                         CC4
*                                                                        CC4
         LDA    =N$A00A          WRITE IN NEXT AVAILABLE LOC. 
         STA*   (SITLOC)         WRITE THE DATA 
         STA*   (SITLOC)         WRITE DATA AGAIN 
         LDA    =N$5400 
         STA-   1                CHANGE INTER REGISTERS 
         LDA*   (SITLOC)         READ BACK DATA 
         EOR    =N$A00A          TAKE AWAY THE DATA OUTPUTED. 
         SAN     PILMT3       SKIP IF NOT ZERO                           CC4
*                                                                        CC4
         STQ*    (SITLOC)     RESTORE TEST LOCATION                      CC4
         LDA*    SIPAGE       TRY NEXT 16K MODULE                        CC4
         INA     SI16KI                                                  CC4
         STA*    SIPAGE                                                  CC4
         INA     -SIPMAX                                                 CC4
         SAZ     PILMT3       SKIP IF HIGHEST POSSIBLE MEMORY TESTED     CC4
         JMP*    PILM25       GO CHECK NEXT PAGE
*                                                                        CC4
* * * SET UP CORE SIZE PARAMETER                                         CC4
*                                                                        CC4
PILMT3   LDQ*    SIPAGE                                                  CC4
         INQ     -1           HIGHEST PAGE VALUE IN EXISTENCE            CC4
         STQ     J1CORESIZE                                              CC4
         LDA*    SI48K        48K MEMORY LIMIT                           CC4
         INQ     -SIPMIN+1                                               CC4
         SQZ     PILMT4       SKIP IF 48K                                CC4
         LDA*    SI65K        65K MEMORY LIMIT                           CC4
PILMT4   ENQ     1                                                       CC4
         STA     J1CORESIZE,Q                                            CC4
*                                                                        CC4
*                                                                        CC4
          ENA    SISVPG       RESTORE PAGE REGISTER USED IN TEST
         ORA*    SITPN                                                   CC4
         WPR     A                                                       CC4
*                                                                        CC4
         JMP*    (PILMT)                                                 CC4
         END                                                             CC4
